Magillem Tool Script

Overview of IP Packaging

Background

Most automated IP integration flows are not truly automated. Only a small number of connections typically well-defined bus interfaces are automatically supported. The majority of interconnections must be made manually or via low-level scripted commands. This approach offers little or no productivity gains over purely manual flows and has very limited potential for reuse. Managing incremental changes as the system evolves is difficult and time-consuming. To resolve the issue, efficient migration to an IP based methodology and flow first requires capture of legacy IP libraries in a technology independent format, using an easy-to-use, scalable and automated process.
The goal of this first step is to package all the components of an IP library into XML files in accordance with the IP-XACT schema (standarized as IEEE1685), which describes the syntax and semantic rules for the description of three kinds of elements: the bus definitions, the components and the designs (in which components are instantiated). Thus the purpose of the IP packaging is to fill in for each component the XML fields that describe its attributes: physical ports, interfaces, parameters, generics, register map, physical attributes, etc. An important part of the schema is dedicated to referencing the files related to the different views of a component: a view may be for instance a simulable model in a specific language (VHDL, Verilog, SystemC, etc) or documentation files (e.g. PDF, HTML, Framemaker). This work facilitates future reuse of existing components, because all of their features are easily accessible for its integration and configuration in a bigger system.

IP-XACT Overview

IP-XACT is an XML schema that defines and describes electronic components and their designs. Goals of IP-XACT are as follow.

·                     To ensure delivery of compatible component descriptions from multiple component vendors

·                     To enable exchanging of complex component libraries between EDA tools for SoC design

·                     To describe configurable components using metadata

·                     To enable the provision of EDA vendor-neutral scripts for component creation and configuration

Advantage of Integration Flow based on IP-XACT

To accelerate the design of complex systems, such as System-on-Chip (SoC), and FPGA based solutions, the IP-XACT standard provides a mechanism for describing and handling multi-sourced IP that enables automated design integration and configuration within multi-vendor tool flows. Also, integration flow using IP-XACT provides a single-source specification from which all design, verification, software and integration teams auto-generate the views they require, thereby remaining perfectly synchronized at all times.

Also, the register centric design-environment using IP-XACT must have the features to handle such synchronization, version handling, data inference. Magillem offers a Register View of Systems and IPs, based on IP-XACT standard, which addresses today’s challenges of HW/SW integration in complex chips.

Magillem - 5.9

Magillem provides a comprehensive front-end EDA environment for intellectual property(IP) packaging, concurrent platform integration, netlist generation, flow execution and register management based on IP-XACT standard (IEEE1685 standard and previous versions), delivered by the Accellera consortium (previously SPIRIT consortium).

<MIP>

Basic Flow of Magillem

There are 2 basic steps in order to setup project before starting methodology flow with Magillem.

1.             Create Project

2.             Import Bus Definition

Create Project

"Project" view, which lists Magillem projects, contains available resources such as components, bus definitions, ...

Procedure) A right-click on the "Project" view background -> Create Project -> Specify Project Name -> Choose version of IP-XACT (IP-XACT 1685) -> Finish

Alternatively:
project::createProject rahul 1685
project::setCurrentProject rahul

Import Bus Definition

project::createResource component rahul ssir ufs sfr 1.0
component::setCurrentComponent {ssir ufs sfr 1.0}

secutil::importBusDef AMBA AHB


Additionally (Optionally)
create_port in  rtl_singal1
create_port in  rtl_singal2 11 0
create_port in  rtl_singal3 15 0
create_port out rtl_singal2


<MIP> - Block Forge

MRV(Magillem Register View)

Depending on the task to be performed, Magillem uses different Eclipse perspective: 
MIP for packaging, 
MPA for assembly and 
MRV for register.

secutil::importSFRExcel \

       -xls [IFMappingExeclFile] \

       -sheet [SheetName] \

       -csv [csvFileName] \

       -baseaddr [BaseAddress] \

       -memname [MemoryMapName] \

       -addrblkname [AddressBlockName] \

       -overwriteopt [MemoryMapName AddressBlockName] \

       -busif [BusI/F Name] \

       -range [digit] \

       -v [version] \

       -remapname [Memory RemapName] It will be available after v1.0.8 release. \

       -remap [Remap PortName/PortValue/PortIndex]

secutil::importSFRExcel -busif <Bus Name> -xls /user/register.xls -sheet rahul -memname <component_name> -baseaddr 0x12345678

Before generating the XML with exportMrvModelComponent
You have to set the parameter _isPresent_ to false

MrvModel::exportMrvModelComponent -vlnv [list V L N V]